Bit-True Stochastic Computing
for Spiking Neural Networks
The only SNN framework with bit-true Python-to-Verilog co-simulation, end-to-end FPGA deployment, and 178 neuron models spanning 82 years of neuroscience. Rust SIMD engine 202× faster than Brian2. Formally verified RTL.
Production Ready Active Development
Train-to-Hardware Pipeline
Complete path from neuron equations to proven silicon. No other SNN framework offers this.
PyTorch SNN
Training
6 surrogates, 12 cells
99.49% MNIST
→
Quantise
Q8.8
Fixed-point
→
SC Bitstream
Simulation
bit-true, LFSR
→
IR Compiler
SystemVerilog
+ MLIR/CIRCT
→
132 Analysis Functions
19 HDL Modules + 72 Formal Properties
HDC/VSA (10K-bit)
Rust SIMD Engine (PyO3) | AVX-512 / AVX2 / NEON / SVE / RVV | 178 Neuron Models | NetworkRunner (160 models, Rayon-parallel)
# ODE → FPGA in one command
sc-neurocore compile "dv/dt = -(v-E_L)/tau + I/C" \
--threshold "v > -50" --reset "v = -65" \
--params "E_L=-65,tau_m=10,C=1" --init "v=-65" \
--target ice40 --testbench --synthesize
What Makes It Unique
◈Bit-true co-simulation — Python matches RTL cycle-exactly with deterministic LFSR seeds and Q8.8 fixed-point.
◈One-command FPGA deploy — sc-neurocore deploy model.nir --target ice40 auto-runs Yosys+nextpnr+icepack.
◈Complete train-to-hardware pipeline — Float → Q8.8 → SC bitstream → Verilog → FPGA.
◈178 neuron models in Rust — Full PyO3 bindings. 160-model NetworkRunner with Rayon-parallel execution.
◈Event-driven FPGA RTL — AER encoder, event neuron, spike router. 15–39× fewer register toggles.
◈6-codec neural compression — 24× waveform, 750× spike raster on 1024-channel Neuralink-scale data.
◈Formal verification — 7 SymbiYosys modules, 72 verified properties. Every HDL module proved correct.
◈Visual SNN Design Studio — Web IDE: equation editor, network canvas, training monitor, compiler inspector, synthesis dashboard.